国外经典Verilog代码

国外经典Verilog代码/* * * Examples from "The Verilog Hardware Description Language", * * by D.E.

国外经典Verilog代码 /* ** Examples from "The Verilog Hardware Description Language", * *by D.E. Thomas and P.R. Moorby ** */ //Example 1.2. NAND Latch To Be Simulated. module ffNand; wire q, qBar; reg preset, clear; nand #1 g1 (q, qBar, preset), g2 (qBar, q, clear); initial begin // two slashes introduce asingle line comment $monitor ($time,, "Preset =%b clear =%b q= %b qBar =%b", preset, clear, q, qBar); //waveform for simulating the nand flip flop #10 preset =0; clear =1; #10 preset =1; #10 clear =0;