门电路VHDL语言

“非”门library ieee;use ieee.std_logic_1164.all;entity not1 isport(a:in std_logic;b:out std_logic);end

“非”门 libraryieee; useieee.std_logic_1164.all; entitynot1is port(a:instd_logic; b:outstd_logic); endentitynot1; architecturebehavofnot1is begin b<=nota; endarchitecturebehav; “与”门 libraryieee; useieee.std_logic_1164.all; entityand2is port(a,b:instd_logic; c:outstd_logic);