FPGA 四位数码管显示

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module LED_Display(clk,seg,dp,an); input clk; // 输入时钟 output[6:0] seg; //7ABCDEFG 个公共段选信号，从低到高对应七段数码管的 output dp; //DP 小数点段选信号 output[3:0] an; //4 位数码管的位选信号 reg [15:0] count_for_clk =0; //,65536 分频计数器分频 reg [3:0] an_reg =0; reg [6:0] seg_reg =0; assign seg=seg_reg; //7 个段选赋值 assign dp=1; // 小数点段选赋值 assign an=an_reg; //4 个位选赋值 parameter //0-9 七段数码管显示数字的段选值 zero =7'b100_0000, one =7'b111_1001, two =7'b010_0100, three =7'b011_0000, four =7'b001_1001, five =7'b001_0010, six =7'b000_0010, seven =7'b111_1000, eight =7'b000_0000, nine =7'b001_0000; // 分频计数器 always@(posedge clk) begin count_for_clk<=count_for_clk+1; end //4 段选寄存器赋值，位数码管分时复用 always@(posedge clk) begin case(count_for_clk[15:14]) 0: seg_reg<=one; //1 数码管段选 1: seg_reg<=two; //2 数码管段选 2: seg_reg<=three; //3 数码管段选 3: seg_reg<=four; //4 数码管段选 endcase end // 位选寄存器赋值，每次只选通一位数码管 always@(posedge clk) begin case(count_for_clk[15:14]) 0: an_reg<=4'b0111; //1 选通数码管 1: an_reg<=4'b1011; //2 选通数码管